Field of the Invention
The present invention relates to a method for producing a semiconductor device and to a semiconductor device.
Description of the Related Art
The degree of integration of semiconductor integrated circuits, in particular, integrated circuits using MOS transistors has been increasing. With the increasing degree of integration, the size of MOS transistors used in integrated circuits has been decreased to nano-scale dimensions. Such a decrease in the size of MOS transistors causes difficulty in suppressing leak currents, which poses a problem in that it is hard to reduce the area occupied by the circuits because of the requirements of the secure retention of necessary currents. To address the problem, a surrounding gate transistor (hereinafter referred to as an “SGT”) having a structure in which a source, a gate, and a drain are arranged vertically with respect to a substrate and a gate electrode surrounds a pillar-shaped semiconductor layer has been proposed (e.g., refer to Japanese Unexamined Patent Application Publication Nos. 2-71556, 2-188966, and 3-145761).
According to a typical method for producing an SGT, a silicon pillar on which a pillar-shaped nitride film hard mask has been formed is formed by using a mask for forming the silicon pillar, a planar silicon layer is formed at the bottom portion of the silicon pillar by using a mask for forming the planar silicon layer, and a gate line is formed by using a mask for forming the gate line (e.g., refer to Japanese Unexamined Patent Application Publication No. 2009-182317). In other words, three masks are used to form a silicon pillar, a planar silicon layer, and a gate line.
In a typical method for producing an SGT, a deep contact hole is formed in order to connect an upper portion of a planar silicon layer and a metal wire (e.g., refer to Japanese Unexamined Patent Application Publication No. 2009-182317). With reduction in the size of devices, the aspect ratio (depth/diameter) of contact holes increases. The increase in the aspect ratio causes a decrease in the etching rate. Furthermore, with reduction in the size of a pattern, the thickness of a resist decreases. If the thickness of the resist decreases, the resist is also etched during etching, which makes it difficult to form a deep contact hole.
A metal gate-last process in which a metal gate is formed after a high-temperature process has been employed in actual production of typical MOS transistors in order to achieve both a metal gate process and a high-temperature process (refer to IEDM 2007, K. Mistry et. al, pp. 247-250). A gate is formed using polysilicon, an interlayer insulating film is deposited, the polysilicon gate is exposed by chemical mechanical polishing and etched, and then a metal is deposited. Thus, a metal gate-last process in which a metal gate is formed after a high-temperature process needs to be also employed in making SGTs in order to achieve both a metal gate process and a high-temperature process.
If an upper portion of a hole is narrower than a lower portion of the hole during filling with a metal, the upper portion of the hole is filled with the metal first, resulting in formation of holes.
In typical MOS transistors, a first insulating film is used to decrease parasitic capacitance between the gate line and the substrate. For example, in a FINFET (refer to IEDM 2010 C C. Wu, et. al, 27.1.1-27.1.4), a first insulating film is formed around one fin-shaped semiconductor layer and etched back to expose the fin-shaped semiconductor layer in order to decrease parasitic capacitance between the gate line and the substrate. Accordingly, the first insulating film needs to be also used in an SGT in order to decrease parasitic capacitance between the gate line and the substrate. Since such an SGT includes a pillar-shaped semiconductor layer in addition to a fin-shaped semiconductor layer, special consideration is required to form the pillar-shaped semiconductor layer.
As the width of a silicon pillar decreases, it becomes more difficult to make an impurity be present in the silicon pillar because the density of silicon is 5×1022/cm3.
In typical SGTs, it has been proposed that the channel concentration is set to be a low impurity concentration of 1017 cm−3 or less and the threshold voltage is determined by changing the work function of a gate material (e.g., refer to Japanese Unexamined Patent Application Publication No. 2004-356314).
It has been disclosed that, in planar MOS transistors, the sidewall of an LDD region is formed of a polycrystalline silicon having the same conductivity type as a low-concentration layer, and therefore surface carriers of the LDD region are induced by the difference in work function and the impedance of the LDD region can be reduced compared with oxide film sidewall LDD-type MOS transistors (e.g., refer to Japanese Unexamined Patent Application Publication No. 11-297984). It has also been disclosed that the polycrystalline silicon sidewall is electrically insulated from a gate electrode. The drawings show that the polycrystalline silicon sidewall is insulated from a source and a drain by an interlayer insulating film.